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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/1005
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dc.contributor.authorKumar, Akashen_US
dc.contributor.authorMazumdar, Bodhisatwa [Guide]en_US
dc.date.accessioned2018-01-24T10:15:11Z-
dc.date.available2018-01-24T10:15:11Z-
dc.date.issued2017-12-05-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/1005-
dc.language.isoenen_US
dc.publisherDiscipline of Computer Science and Engineering, IIT Indoreen_US
dc.relation.ispartofseriesBTP295;CSE 2017 KUM-
dc.subjectComputer Scienceen_US
dc.titleOptimization of majority-inverter gate logic over and-or-inverter gate logicen_US
dc.typeB.Tech Projecten_US
Appears in Collections:Department of Computer Science and Engineering_BTP

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