Scaling limits of capacitorless DRAM implemented through twin-gate reconfigurable transistor

Abstract

As we moved through the age of machine learning, big data and Artificial Intelligence (AI), the requirements for computations have increased drastically. So has the requirement of memory. As per Moore’s law and Dennard’s scaling theory, number of transistors per unit chip has been doubled every 18 months with the advantages of low power as well as high speed. However, the overall system performance which depends on the interaction between the processor and memory did not improve at the same speed due to a lack of innovation in the memory segment. So, in recent decades, a lot of research has been done on the improvement of speed and density of memory for high power as well as low power applications. Although the conventional 1T-1C Dynamic Random Access Memory has dominated the market for a sufficiently long time, the unscalable nature of the capacitor along with the short channel effects, dielectric leakage, gate induced drain leakage, diode leakage affect the performance of the device significantly. This begs to look into the possibilities of using different device architectures such as using the body of transistor itself (1T) to store the charges in order to overcome the difficulties faced by 1T-1C DRAM. The conventional partially depleted and fully depleted structures have been studied and shown promises as 1T-DRAM. However, integration of processor along with memory on the same chip for low power and high-speed application requires devices that can offer more than simple logic implementation. Thus, the thesis work focuses on an energy-efficient device, Reconfigurable Field Effect Transistor Tunnel (RFET) as 1T-DRAM, which can also be used for logic implementation with a lesser no of transistors due to its inherent reconfigurable nature.