Hardware neural accelerator implementation for IoT based applications

Abstract

In recent years, on-chip Neural Network Accelerators have grown in popularity as one of the best algorithms for numerous key detection and classification problems in image, speech, and a variety of other never-ending applications in intelligent system design. While their on-chip presence is desirable, their high computational demands continue to be a roadblock in the development of the next generation of System on Chips. Although hardware accelerators for Convolutional Neural Networks are frequently simple designs, a traditional design approach has not been very successful, as they often require a lot of silicon area and power. Fixed point processing, according to researchers, can result in a large reduction in resource use while having a negligible influence on accuracy. Many issues that are challenging for other computational models, such as image processing, pattern recognition, prediction, and classification, are well-suited to a Convolutional Neural Network. Hardware designs can feature a more parallel structure of CNNs to improve performance or lower implementation costs, especially for applications that require high parallel computation. However, hardware platforms have a lot of unique disadvantages, including limits with high data precision, which is related to the hardware cost of the necessary computation, and the hardware implementation's lack of reconfigurability compared to software. Due to resource-intensive parts such as multipliers, current Convolutional Neural Network hardware implementations have an excess area need. The present work addresses this challenge by proposing a Co-ordinate Rotation Digital Computer (CORDIC)- based neuron architecture (RECON) implemented using In-SRAM In-Memory Computing and modified Static Manchester Carry Adder, which can be configured to compute multiply accumulate (MAC). The CORDIC-based architecture uses linear relationship to realize MAC, whereas CORDIC algorithm uses minimum resources to realize different mathematical operations. The CORDIC architecture is area and power efficient with the overhead of lower throughput. In this project, we propose a Pipelined CORDIC based MAC using In-Memory Computing and modified Static Manchester Carry adder. This proposed design significantly increases the throughput by 40% when compared with conventional methods. Choosing 8-bit precision improves the power consumption and area utilization. When operated at 1V, the power consumption decreases by 38%. Hence, the proposed design offers the best throughput among the state of art and consumes lesser power and area when designed at 8-bit precision and operated at 1 V.