Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/10326
Title: Reducing computational complexities using GPU and FPGA
Authors: Verma, Harshit
Supervisors: Vasudevan, Srivathsan
Bulusu, Satya S.
Keywords: Electrical Engineering
Issue Date: 9-Jun-2022
Publisher: Department of Electrical Engineering, IIT Indore
Series/Report no.: MT182
Abstract: Computationally intensive applications such as weather forecasting, computational biology, Molecular Dynamics etc. requires a lot of time to execute a task, because usually these tasks are sequentially executed. Because the iterative nature of these algorithms on a single CPU can take up a lot of computation time for relatively basic simulations, there's a lot of pressure to find ways to improve efficiency. As a result of present processor technology's clock restrictions, improved computer performance is becoming increasingly reliant on parallelism. This project deals with exploring the different ways in which parallelism can be inherited for calculations of Interatomic potentials of gold nanoparticle. Phase 1 of the research focuses on computing on GPUs, which can drastically speed up computer applications by leveraging GPU capabilities. The sequential component of the workload in GPU-accelerated applications operates on the CPU, which is tuned for single-threaded speed, while the compute-intensive portion of the application runs in parallel on thousands of GPU cores. A portion of complex algorithm is thereby studied and parallelized and subsequent comparative analysis is done to observe whether the results are obtained accordingly or not. Phase 2 of the project deals with the computations being carried out on FPGA and establishing communication between PC and FPGA using PCIe protocol. Input data from host PC is first sent to FPGA where various calculations such as force, energy values is being done and these values are then sent back from FPGA to host PC and this process is done iteratively by defining the number of steps. Finally, the total time taken in these steps is calculated. The primary goal of our work is to reduce the computational time taken by sequential C code of complex algorithm with the help of Parallelism using GPU and FPGA.
URI: https://dspace.iiti.ac.in/handle/123456789/10326
Type of Material: Thesis_M.Tech
Appears in Collections:Department of Electrical Engineering_ETD

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