Insights Into Parasitic Capacitance and Reconfigurable FET Architecture for Enhancing Analog/RF Metrics

Abstract

Through an insightful analysis of different architectures of reconfigurable field-effect transistor (FET) (RFET), the work showcases its potential to achieve improved voltage gain (AV), cutoff frequency (fT), and gain-bandwidth product (AV × fT) at low current levels. The extraction of parasitic components reveals lower total parasitic capacitance (Cparasitic) in RFET as compared to a double gate (DG) MOSFET for the same total length (LT) despite a greater number of gates. While a twin-gate RFET architecture is more suitable for high-gain applications, a three-gate RFET topology is more favorable for larger bandwidth. The flexibility to optimize control gate (CG) length (LCG), ungated length (LUG), and polarity gate (PG) length (LPG) for the same LT can be best utilized through a three-gate RFET with LCG/LT≥0.4 and LUG/LT = 0.1 to attain high values of both fT and AV as compared to MOSFET. Results provide new viewpoints for optimizing analog/RF metrics at low current levels through twin-gate and three-gate RFETs. © 1963-2012 IEEE.