Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/13119
Title: Evaluation of Leakage Currents in Memristor Crossbar Arrays
Authors: Kumar, Mukesh
Keywords: CMOS;crossbar array;leakage or sneaky current;LTspice;Memristor;nMOS;pMOS;sneaky path current
Issue Date: 2023
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Kasongo, M., Ytterdal, T., Lee, J., Rizkalla, M., & Kumar, M. (2023). Evaluation of Leakage Currents in Memristor Crossbar Arrays. Proceedings of the IEEE National Aerospace Electronics Conference, NAECON. Scopus. https://doi.org/10.1109/NAECON58068.2023.10365978
Abstract: Memristors are novel electronic devices. Memristor-based crossbar arrays have gained a lot of attention for potential applications in nonvolatile memory, in-memory computing, logic design, neuromorphic computing systems, and neural networks. In this paper, we demonstrate the sneaky path current issue within a 3×3 crossbar array. 1T1M scheme has been used to reduce the leakage current. Integrating nMOS and pMOS devices in series with memristors in the crossbar array has optimized the leakage currents. The results show that nMOS devices reduce the leakage currents by 97.35%, whereas pMOS devices reduce the leakage currents by 92.20%. Thus, nMOS outperform pMOS devices in leakage currents optimization. © 2023 IEEE.
URI: https://doi.org/10.1109/NAECON58068.2023.10365978
https://dspace.iiti.ac.in/handle/123456789/13119
ISBN: 979-8350338782
ISSN: 0547-3578
Type of Material: Conference Paper
Appears in Collections:Department of Electrical Engineering

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