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| Title: | Extremely High Noise Margin and Low Leakage in ULP Circuits with NCFETs |
| Authors: | Semwal, Sandeep Nirala, Rohit Kumar Kranti, Abhinav |
| Issue Date: | 2024 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Semwal, S., Nirala, R. K., Gupta, M., & Kranti, A. (2024). Extremely High Noise Margin and Low Leakage in ULP Circuits with NCFETs. 2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings. https://doi.org/10.1109/VLSITSA60681.2024.10546420 |
| Abstract: | The efficacy of negative capacitance transistors (NC-T) to implement ultralow power (ULP) subthreshold logic blocks such as inverter, diode, composite transistor (CT) based diode, n-type and p-type CT, and CT inverter is reported through simulations and analytical model. ULP logic blocks with NC-T are shown to exhibit (i) improved noise margin ( 80% of supply voltage (VDD)), (ii) wider hysteresis window ( 0.9 VDD), (iii) suppressed reverse saturation current (10-14 A) in CT diode, and (iv) signif-icantly lower off-current (∼8 ×10-15 A) in n-type CT. © 2024 IEEE. |
| URI: | https://doi.org/10.1109/VLSITSA60681.2024.10546420 https://dspace.iiti.ac.in/handle/123456789/14237 |
| ISBN: | 979-8350360349 |
| Type of Material: | Conference Paper |
| Appears in Collections: | Department of Electrical Engineering |
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