Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/14368
Full metadata record
DC FieldValueLanguage
dc.contributor.advisorVasudevan, Srivathsan-
dc.contributor.advisorBulusu, Satya S-
dc.contributor.authorKartikey, Dharmendra-
dc.date.accessioned2024-09-06T12:10:28Z-
dc.date.available2024-09-06T12:10:28Z-
dc.date.issued2024-05-24-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/14368-
dc.description.abstractMolecular dynamics (MD) simulations involve calculating the forces Between atoms and the total energy of chemical system; however, these computations typically rely on high-end, sequential, and power-intensive servers. This poses a limitation when attempting to simulate large-scale systems that are relevant to real-world experiments. To address this challenge, An Artificial Neural Network (ANN) method to compute interatomic forces and energy in a system consisting of 147 Au atoms was created and it was implemented on a FPGA system. Existing approach involves a combination of parallel computation on a Field Programmable Gate Array (FPGA) and simple computations performed on a Host PC. Effective communication between the Host PC and the FPGA is crucial for the success of this hardware- software co-design. This Thesis is an exploratory thesis which tries to explore new methods of time performance improvements over existing approach. It investigates interrupt-based transmission and CDMA based data transfer method to improve time performance of existing design. Detailed comparative test cases have been devised to come to a quantitative conclusion. At the end it proposes a Lab-on-a-chip architecture for Molecular dynamics cycle for enhancing time performance by eliminating inter-device communication like UART/Ethernet and making design more compact. It also covers basic design challenges in the Lab-on-a-chip architecture and provides solutions and test cases for validation of those solutions.en_US
dc.language.isoenen_US
dc.publisherDepartment of Electrical Engineering, IIT Indoreen_US
dc.relation.ispartofseriesMT305;-
dc.subjectElectrical Engineeringen_US
dc.titleHigh performance computing using FPGAen_US
dc.typeThesis_M.Techen_US
Appears in Collections:Department of Electrical Engineering_ETD

Files in This Item:
File Description SizeFormat 
MT_305_Dharmendra_Kartikey_2202102027.pdf3.71 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

Altmetric Badge: