Please use this identifier to cite or link to this item:
https://dspace.iiti.ac.in/handle/123456789/14368
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Vasudevan, Srivathsan | - |
dc.contributor.advisor | Bulusu, Satya S | - |
dc.contributor.author | Kartikey, Dharmendra | - |
dc.date.accessioned | 2024-09-06T12:10:28Z | - |
dc.date.available | 2024-09-06T12:10:28Z | - |
dc.date.issued | 2024-05-24 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/14368 | - |
dc.description.abstract | Molecular dynamics (MD) simulations involve calculating the forces Between atoms and the total energy of chemical system; however, these computations typically rely on high-end, sequential, and power-intensive servers. This poses a limitation when attempting to simulate large-scale systems that are relevant to real-world experiments. To address this challenge, An Artificial Neural Network (ANN) method to compute interatomic forces and energy in a system consisting of 147 Au atoms was created and it was implemented on a FPGA system. Existing approach involves a combination of parallel computation on a Field Programmable Gate Array (FPGA) and simple computations performed on a Host PC. Effective communication between the Host PC and the FPGA is crucial for the success of this hardware- software co-design. This Thesis is an exploratory thesis which tries to explore new methods of time performance improvements over existing approach. It investigates interrupt-based transmission and CDMA based data transfer method to improve time performance of existing design. Detailed comparative test cases have been devised to come to a quantitative conclusion. At the end it proposes a Lab-on-a-chip architecture for Molecular dynamics cycle for enhancing time performance by eliminating inter-device communication like UART/Ethernet and making design more compact. It also covers basic design challenges in the Lab-on-a-chip architecture and provides solutions and test cases for validation of those solutions. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Department of Electrical Engineering, IIT Indore | en_US |
dc.relation.ispartofseries | MT305; | - |
dc.subject | Electrical Engineering | en_US |
dc.title | High performance computing using FPGA | en_US |
dc.type | Thesis_M.Tech | en_US |
Appears in Collections: | Department of Electrical Engineering_ETD |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
MT_305_Dharmendra_Kartikey_2202102027.pdf | 3.71 MB | Adobe PDF | View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
Altmetric Badge: