Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/14368
Title: High performance computing using FPGA
Authors: Kartikey, Dharmendra
Supervisors: Vasudevan, Srivathsan
Bulusu, Satya S
Keywords: Electrical Engineering
Issue Date: 24-May-2024
Publisher: Department of Electrical Engineering, IIT Indore
Series/Report no.: MT305;
Abstract: Molecular dynamics (MD) simulations involve calculating the forces Between atoms and the total energy of chemical system; however, these computations typically rely on high-end, sequential, and power-intensive servers. This poses a limitation when attempting to simulate large-scale systems that are relevant to real-world experiments. To address this challenge, An Artificial Neural Network (ANN) method to compute interatomic forces and energy in a system consisting of 147 Au atoms was created and it was implemented on a FPGA system. Existing approach involves a combination of parallel computation on a Field Programmable Gate Array (FPGA) and simple computations performed on a Host PC. Effective communication between the Host PC and the FPGA is crucial for the success of this hardware- software co-design. This Thesis is an exploratory thesis which tries to explore new methods of time performance improvements over existing approach. It investigates interrupt-based transmission and CDMA based data transfer method to improve time performance of existing design. Detailed comparative test cases have been devised to come to a quantitative conclusion. At the end it proposes a Lab-on-a-chip architecture for Molecular dynamics cycle for enhancing time performance by eliminating inter-device communication like UART/Ethernet and making design more compact. It also covers basic design challenges in the Lab-on-a-chip architecture and provides solutions and test cases for validation of those solutions.
URI: https://dspace.iiti.ac.in/handle/123456789/14368
Type of Material: Thesis_M.Tech
Appears in Collections:Department of Electrical Engineering_ETD

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