A Survey of High Level Synthesis based Hardware (IP) Watermarking Approaches

Abstract

The paper presents a novel survey of high level synthesis (HLS) based hardware intellectual property (IP) watermarking approaches. It includes a crisp analytical assessment of all the major HLS watermarking techniques employed for reusable IP cores. The paper starts off with a quintessential background on hardware watermarking, followed by the vital properties of a strong watermark. It seamlessly progresses into the discussion on the pivotal phases of HLS hardware watermarking including highlights on watermark insertion sites and its verification/validation process. The paper also encompasses the taxonomy of major diverse HLS watermarking techniques, published in the community, followed by a detailed presentation of the hardware watermarking approaches in terms of their design flow, advantages and limitations. Moreover, a qualitative and quantitative analysis of different HLS watermarking techniques assessed in terms of security (tamper tolerance, probability of coincidence, and attacker&#x2019

s effort) and watermarking design overhead, is also presented. Finally, the paper concludes by also providing the pointers on future directions in the field of hardware watermarking. IEEE