Performance enhancement of 3D cylindrical gate-all-around tunnel FET and its applications for ultra low power cross coupled voltage doubler circuit design

Abstract

Today’s market of semiconductor industry influenced by assertive scaling leads to the requirement of low power devices. However, conventional MOS field effect transistor (MOSFET) scaling in order to maximize on-die functionality has had a significant detrimental impact on leakage-dominated OFF-current. This is because of its sub threshold slope (SS), governed by thermionic emission-carrier diffusion over a thermal barrier being limited to 60 mV/decade (SS= (kT/q) × ln10) at room temperature. Further the demand of circuit application needs ultra-low power consumption to utilize battery for longer duration. Although, scaling down of MOSFET supply voltage is very difficult without significantly increasing the subthreshold leakage current. As a result, a tradeoff exists between the ability to operate in the subthreshold regime while simultaneously maintaining low-power dissipation. This limitation is challenging for low supply voltages and making it unsuitable for analog/RF applications. Therefore, for next generations of integrated circuits, there is a need for ultra-low-power and energy-efficient transistors with steepest SS.In this regard, the devices based on the inter-band tunneling such as Tunnel Field effect transistor (TFET) appear as a prominent novel device for low-power application over conventional MOSFET. This is because of their attractive properties of low SS, caused by the different carrier conduction mechanism based on band-to-band tunneling (BTBT). This enables low standby leakage currents and further scaling of supply voltage (Vdd), makes it suitable for low power module of IoT applications contains analog/RF and digital blocks. In addition with low off current, high current driving capability is also required to produce attractive analog/RF characteristics. In this concern, an optimized Tunnel FET structure that can improve driving current as well as analog/RF characteristics without an increase in IOFF is of great importance for low power module of IoT applications. Therefore, in this thesis, we have investigated the device design and circuit performance of a 3D Cylindrical (Cyl) gate all around (GAA) Tunnel FET. In this 3D structure, gate is wrapped all around the channel, which increases the tunneling rate between source/channel junction and significantly, supports for high driving current. Here, we will explore methods to improve analog/RF performances of the 3D Cyl Gate-All-Around Tunnel FET using a spacer and underlap engineering for low power applications. Further, wehave extended our analysis towards the analog/RF performances and circuit design for a low power Cross Coupled Voltage Doubler (CCVD). Initially, we have calibrated the examined device with experimental published data and investigated the comparative device performance for the three structures of Cyl GAA-Tunnel FET in terms of DC characteristics such as ION, IOFF, SS, and ION/IOFF. Here the design and physics of the examined device was mainly focused to achieve low subthreshold leakage and ambipolar behavior without affecting high ION, using the concept of low spacer width and asymmetry in underlap. Here, it is found that asymmetry in underlap with low spacer width produces the best device performance regarding DC characteristics. In continuation of chapter 2, we have presented the investigations of Cyl GAA-TFET based on Ge-source for improved analog/RF characteristics. Here, physics of fringing field was implemented using hetero-spacer dielectric with merits of low band gap material such as Ge, which increases the tunneling rate by reducing the barrier width of junction and is a feature for enhanced DC and Analog/RF characteristics such as ION, IOFF, SS, Cgs, Cgd, gm, ft, and fmax. Besides, the high performances of the examined device, reliability is also an important concern, Therefore, we have presented the effects of Trap-Assisted Tunneling (TAT) on Cylindrical GAA-Tunnel FET based on hetero-spacer engineering for improved device reliability. Here, impact of trap charges have been studied while incorporation of TAT physical model for theanalysis of experimental/ fabrication non-idealities caused by heavy doping, phonons and high radiations. Finally, I have comprehensively investigated the circuit performance parameters of the proposed device using device-circuit co-approach while design a CCVD for low power IoT sensor node.