SecureHD: Designing Low-Cost Reliable and Security Aware Hardware Accelerators During High-Level Synthesis for Computationally Intensive Application Frameworks

Abstract

Reliable and low-cost hardware accelerator design and its security countermeasures are crucial to safeguard not only the end consumer but also the intellectual property (IP) vendor and system-on-chip (SoC) integrator. The reusable hardware accelerator-based design paradigm has become popular for its usage in several consumer electronics (CE) and computing systems. This is because the usage of hardware accelerators enables higher performance and efficacy by accelerating the underlying computationally-intensive application frameworks. In the proposed work, secure hardware accelerators for digital signal processing (DSP), multimedia and machine learning frameworks are designed (at zero design overhead) during high-level synthesis (HLS) as it offers lesser design complexity than lower levels of chip design. Further, HLS facilitates to integration of modules for design space exploration and integrating multi-layer security. The proposed methodologies offer the following: (a) hardware accelerator design for various computationally intensive application frameworks (b) negligible design cost overhead (c) seamless detective control against counterfeiting (d) higher tamper tolerance (e) low probability of false positive (f) higher strength of obfuscation to thwart reverse engineering attack. © 2024 IEEE.