Please use this identifier to cite or link to this item:
https://dspace.iiti.ac.in/handle/123456789/1648
Title: | Performance enhancement of CMOS digital circuits strain engineered asymmetric dual-k spacer FinFETs |
Authors: | Gopal, Maisagalla |
Supervisors: | Vishvakarma, Santosh Kumar |
Keywords: | Electrical Engineering |
Issue Date: | 1-May-2019 |
Publisher: | Department of Electrical Engineering, IIT Indore |
Series/Report no.: | TH200 |
Abstract: | In scaled technologies multi-gate MOSFETs are become the promising candi- dates to replace the bulk MOSFET due to their reduced Short Channel E ects (SCEs) and higher current driving capabilities. Among all the multi-gate MOSFETs, quasi planar double gate (FinFET) device architecture has attracted much attention of today's VLSI industry because of it's fabrication simplicity and scalability. We propose silicongermanium (SiGe)/Si carbide (SiC) source/drain (S/D) asymmetric dual-k spacer underlap Fin-Field-E ect Transistor (SiGe/SiC-AsymD-k FinFET) with Si channel. Strain-induced mobility enhancement due to the Si1xGex/Si1yCy S/D leads to a signi cant drive current enhancement of the proposed device. The introduced dual-k at source side helps to achieve unequal magnitudes in current driving capabilities based on the applied positive and negative drain bias. In this thesis, we particularly focused on 6T SRAM cell to mitigate the read-write con- ict. We show that using this unique technology feature of the proposed device, the read-write con ict can be mitigated in 6T SRAM cell and achieve higher cell stability. Simulation results show that SiGe/SiC-AsymD-k FinFETs based SRAM o ers 14.28% and 18.06% improvement in read and write mode respectively over conventional FinFET based 6T SRAM bit cell. When compared to conventional FinFET 6T SRAM bit cell, the proposed 6T SRAM bit cell shows lesser temper- ature sensitivity of cell stability. We report the reliability aspects of the proposed deice. We also explore the SiGe channel based AsymD-k FinFET for high perfor- mance and robust SRAM cell. The amalgamation of channel mobility enhancement and asymmetric dual-k, o ers high current drive capabilities while preserving lower short channel e ects. This results in improvement of Static Noise Margin (SNM) of all possible modes of SRAM. Compared to conventional FinFET SRAM, SiGe based AsymD-k FinFET SRAM exhibits 9.16% enhancement in hold SNM, 18.22% in read and 5.96% in write SNM. Furthermore, the read and write access times reduced by 48.6% and 32.4% respectively. |
URI: | https://dspace.iiti.ac.in/handle/123456789/1648 |
Type of Material: | Thesis_Ph.D |
Appears in Collections: | Department of Electrical Engineering_ETD |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
TH_200_Maisagalla Gopal_1401102008.pdf | 2.74 MB | Adobe PDF | ![]() View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
Altmetric Badge: