Transistor architecture evaluation for standalone and embedded IT-DRAM

Abstract

For the past few decades, scaling of the transistor for higher speed and dense memory with lower cost per bit has been successfully achieved by semiconductor memory industries. The increase in demand for innovative applications has further stimulated the development of novel memory technologies. The Dynamic Random Access Memory (DRAM), which is the main memory for desktop and larger computers due to its high density, low latency and low cost, is facing physical limitations and process complexity in the nanoscale regime. The reduction in size of the capacitor in a conventional DRAM (1T-1C DRAM) adversely affects the charge retention, requires more refresh cycles, and consequently, dissipates more power. The problem can be circumvented with the use floating body of Silicon-on-Insulator (SOI) of the single transistor (1T) as DRAM cell. However, the scaling of conventional SOI Metal-Oxide-Semiconductor FETs (MOSFETs) suffers from Short Channel Effects (SCEs), Band-to-Band Tunneling (BTBT) along with the formation of ultrsharp pn junction in nanoscale regime. Although conventional SOI MOSFET based 1T-DRAMs have shown promising results, the issue of formation of ultrsharp pn junction and SCEs in nanoscale regime are quite challenging. Thus, the focus has shifted towards use of devices with a without junction and operatation at lower drain bias as compared to Inversion Mode (IM) transistors. Junctionless (JL) transistors overcome the issue of formation of ultrasharp junction and SCEs in nanoscale transistor compared to other pn junction based transistor. Thus, the thesis work focuses on different JL architectures for standalone and embedded capacitorless DRAM (1T-DRAM) with improvement in its metrics such as Retention Time (RT), Sense Margin (SM), Current Ratio (CR), speed, and scalability at low lower bias. JL transistorhas shown the possibility as 1T-DRAM. However, it achieves much lower RT (RT < 64 ms, a target specified by International Technology Roadmap for Semiconductors (ITRS)). Therefore, a careful reinvestigation is required for JL architecture as DRAM with its operation and requirement to enhance the performance metrics with modification of device architecture for standalone and embedded DRAM (eDRAM). The work in the thesis provides physical insights into the understanding of the performance and behavior of JL devices for memory applications through device simulations.The key contribution of this research is the evaluation of device architecture for standalone and embedded DRAM applications. The DRAM metrics decide the application, therefore, the thesis work demonstrates device perspective, where various metrics of DRAM are regulated by device architecture (double gate, stacked, and shell-doped), geometry (gate lengths, film thickness), parameters (oxide thickness, gate workfunction), biases and temperature. These DRAM metrics are governed through hole generation and recombination in the storage region that defines distinct operations (Write, Hold and Read) of DRAM.The doping dependent analysis showcasing the carrier lifetime and potential depth modulates DRAM metrics of conventional Junctionless architecture for standalone and embedded DRAM applications. The independent gate operation of JL transistor utilizes the front gate (Gate1) for conduction and back gate (Gate2) for charge storage. The depletion of electrons from the silicon film forms a profound potential well, and therefore, enhances the retention characteristics. The moderate doping (Nd) in the channel, longer underlap length (Lun) and higher gate workfunction (φm) shows the applicability for standalone memory with higher RT while higher doping can be utilized for eDRAM with high speed. Results highlight a high retention of ~2.5 s at 85 °C and ~4.5 s at 27 °C for a gate length (Lg) of 400 nm and Nd of 1017 cm-3 with scalability down to 25 nm (RT > 64 ms, target specified by ITRS). The variation in channel doping shows a reduced retention with increased doping, but higher doping can be used for high speed and low power consumption in an embedded memory. Insights into doping dependent characteristics for AM and JL devices along with storage volume analysis presents new viewpoints for efficient memory operation. TheStacked junctionless (SJL) architecture consists of an n-type and p-type regions separated by an oxide. The functionality of architecture as DRAM is based on physically decoupling the conduction region (top n-type JL transistor) and storage region (bottom p-type JL), while maintaining an electrostatic coupling between them. The use an of oxide layer (SOX), separating the conduction and storage regions, reduces the hole recombination as the stored holes are away from heavily doped n++ Source and Drain regions, and also, reduced generation of holes, and thus, can enhance RT. SJL transistor enhances RT of 1T-DRAM, with a significant improvement (~×103) as compared to a conventional JL transistor with a doping (Nd) of 1019 cm-3 and Lg of 200 nm at 85 °C. SJL based 1T-DRAM achieves maximum RT of ~2.5 s for Nd = 5×1018 cm-3 and ~1 s for 1019 cm-3 with Lg of 200 nm at 85 °C. Results demonstrate its functionality down to 20 nm. The work showcases the possibilities of achieving higher retention time through an appropriate optimization of the architecture.While SJL topology achieves a higher RT it requires more time to perform write operation due to the separation of storage region from the conduction. Shell-Doped (SD) topology is an optimal choice to overcome the trade-off between DRAM metrics. Shell-Doped topology with a thin heavily doped shell and a thicker (intrinsic) core achieves a deeper potential well, and thus, enhances the performance of 1T-DRAM. The advantage in terms of high RT in SD topology is due to enhanced depletion of electrons that facilitates a deeper potential well for charge storage and reduces the diffusion and recombination of generated holes. The work also investigates the dependence of shell thickness (TShell) and doping (Nd) on physical mechanisms associated with RT and Sense Margin (SM), current ratio and speed. Additionally, the impact of gate length scalability and high temperature on RT is shown. Results highlight the possibility of achieving enhanced RT in SD JL devices at lower gate lengths through appropriate selection of device parameters and optimization.The work presented in the thesis showcases new viewpoints for JL devices to function as dynamic memory. The physical insights and analysis of different attributes with optimal utilization of each can lead to improved metrics as well as suppressed trade-offs. Further, the feasibility assessment of the proposed DRAM for standalone and embedded applications is presented through the evaluation of key performance metrics.