Design optimization of pMOS only eDRAM macro cell at 28 nm node

Abstract

Embedded DRAM (eDRAM) architectures have been driven by growing need for energy-efficient and high-density memory. The 2-Transistor 0 Capacitor (2T0C) Gain Cell (GC) appears as compact logic compatible substitute for traditional 1T1C DRAMs. However, a main drawback of the 2T0C GC is its low Data Retention Time (DRT), which is primarily degraded due to capacitive coupling and leakage currents at advanced technology nodes. This thesis explores an effective approach to enhance DRT by using Double Gate (DG) topology with 2T pMOS-only GC structure at the 28 nm technology node. DG transistors offer better electrostatic control over the channel, boost driving current and reduced leakage current, and tunable threshold voltages through independent gate operation, all of which are crucial for GC. Important contribution of this thesis includes a two-step DRT enhancement approach. First, minimizing capacitive coupling by independent gate bias operation to allow a larger voltage difference (ΔV) between to logic levels. Second, suppressing leakage by degradation rate. The thesis work also analyses the effects of high temperature operation and supply voltage downscaling on DRT.