A critical assessment of realizing capacitorless dram with innovative reconfigurable mosfets

Abstract

The evolution of transistor architecture from conventional planar to three-dimensional vertical nanosheet or nanowire coupled with innovation through low power Silicon-on-Insulator (SOI) technology has largely contributed to enhancing transistor density in modern chips. Despite critical innovations in transistor architecture and reduction of parasitic components, a fundamental limitation of Complementary Metal Oxide Semiconductor (CMOS) technology is the requirement of separate n-type and p-type transistors to implement logic circuits. If the polarity (type of transistor) could be obtained through bias in the same structure (device) then separate transistors would not be needed for implementing logic circuits. A three gated (3-gated) reconfigurable MOSFET, also known as reconfigurable field effect transistor (RFET), permits selective carrier injection through modulation of metal-semiconductor (M-S) Schottky contact with an additional gate for channel control.