Predictive clock skew redistribution methodology for improving timing QoR

Abstract

In modern technology with shrinking size and high speed requirement there is a need of an efficient design flow. The traditional method of synthesis doesn’t take into account of clock skew scheduling that’s going to be happening in Clock Tree building and optimization stage. In order to meet the timing specification synthesis, tries to optimize the data path. Although this method will improve setup violation but impact area and power on the overall design. On the other hand, positive slack distributed in our design is not utilized. To solve this issue many have proposed a Back-annotation [BA] flow. In BA, useful skew number is retrieve from CTS stage and feedback either to CTS or synthesis stage. This long feedback loop from the implementation tool to synthesis not only impact the design time cycle but also result in an inefficient result as the implementation is already done keeping data path optimization in mind.In this project we will discussed a methodology on how this positive slack can be retrieved by adjusting the clock skew at synthesis stage and redistributed along the most critical path in our design. The proposed algorithm analyze slack across multiple depth of a timing path and redistribute the available slack by adjusting the clock skew of capture or launch registers to the most critical register pair. The clock skew adjustment script which will be our output will be passed down to physical implementation tool at placement and clock tree synthesis stage so that skew aware placement and clock tree build happen which will result into better timing correlation between the synthesis tool and implementation tool.The proposed system leads to improve runtime and timing QoR of design. Power and area reduction over conventional method of zero skew synthesis is also observed. Moreover, the flow is generic which means that whenever there is a technology shift no reconfiguration is required as the flow is independent on the technology parameter.