Predictive clock skew redistribution methodology for improved timing QoR

Abstract

The functionality of a digital IC depends upon whether its design meets the required timing specifications or not. Though meeting these timing requirements remains a priority throughout the physical design flow but the final design step which specifically deals with meeting these requirements is timing closure.The conventional way of meeting these timing specifications is by adjusting the data path delay. Data path is made faster to fix the setup timing violations. Though this methodology is able to fix setup violations but it has a disadvantage as it increases the area and power consumption of the design. This technique doesn’t uses the positive slack available in the design , so the available positive slack becomes a wastage during timing closure and this can also limit the speed of the design. During timing closure, when such available slacks are recovered and used, then use of standard cells having low threshold voltage is also reduced. Hence distribution of such positive slack improves overall system performance. The work presented in this thesis talks about an algorithm which predicts the positive slack available across the design during synthesis and then redistribute these slack values across timing critical paths to remove their timing violations. These skew values are later used during physical implementation of design so that placement of cells is done in accordance with these skew values. This also helps the design to operate at high frequency. The results shows better timing QoR as we see reduction in total negative slack, worst negative slack and also in the number of violated timing paths. Runtime increases compared to the conventional methodology but not by a significant amount.