On-chip circuit design techniques for high-speed serial links

Abstract

Advances in semiconductor manufacturing allow higher degree of integration for application-specific integrated circuits (ASIC). The high transmission bandwidth requires an interface system to match the error-free transmission and communication need. The high speed computing and communication network advancement require scaling of silicon technology for higher number of component integration on small chip area and low power consumption. Serial Link Transceivers is the crucial element in achieving high data transmission with I/O pin limitations in systems-on-chips (SoCs) and ASIC’s. To match this high speed data computing requirements, power consumption and data recovery becomes key aspects. The focus of this thesis is on the circuit design of serial links using different methods of serialization. A new serial link transceiver design is presented for high-speed synchronous transmission. The design consists of Wave Combining and driving unit at the transmitter end and the Decombiner at the receiver end. Wave combining and driving unit is responsible for combining the different serial data streams, and its driving over the transmission channel respectively. In contrast, a decombiner separates the information according to the clock signal. Continuous-Time Linear Equalizer (CTLE) taps help to limit the jitter tolerance up to 10% of the data received. The other commonly used serial link method is the asynchronous transmission. The asynchronous serial links are independent of a clock. The handshake protocols in asynchronous transmission method ensure valid data transmission. Furthermore, handshaking signals slow down the circuit, so the current mode logic blocks are used for faster transmission of the signal. To help in asynchronous data serial link communication, an improved Current Mode Logic (CML) latch design is proposed. The Improved CML latch results in a boost in the output voltage swing, the delay model of latch is also proposed, based on the small-signal equivalent circuit analysis for the proposed latch. As an application of CML latch, asynchronous Wave-Pipelined Serial link is proposed. In designing of a serializer and deserializer is built using proposed CML Latch. The CML circuit operates at a higher data rate and low power consumption.