Design optimization of double gate junctionless MOSFET for enhanced short channel immunity

Abstract

The semiconductor industry has continuously been involved in the development and production of digital Integrated Circuits (ICs) for High Performance (HP) and Low Power (LP)/Ultra Low Power (ULP) logic applications. Due to the very different nature of constraints, LP compatible devices widely differ from the HP transistor architectures. The prime goal of LP technology is to trade-off speed performance for low standby power or low off-current (IOFF). A scaled-down transistor possessing ideal subthreshold swing (S) and a low value of Drain Induced Barrier Lowering (DIBL) is desirable for LP technology. However, due to the downscaling of the gate length (Lg), the undesirable Short-Channel Effects (SCEs) are observed in the characteristics of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). SCEs cause a reduction in threshold voltage (Vth) with decreasing Lg (i.e. threshold voltage roll-off, dVth) and increasing Vds (i.e. DIBL), as well as degradation in S. A feasible solution to alleviate SCEs is to enhance electrostatic control over the channel region through multiple gates in a transistor. Multi-gate Junctionless (JL) transistors can be potential alternatives to conventional MOSFET for downscaling owing to the absence of traditional pn junctions, relaxed fabrication processes and thermal budgets, efficient control over the channel by multiple gates, and enhanced immunity towards SCEs. Literature has shown the potential of heavily doped (1019 cm-3) JL MOSFET over conventional MOSFET for LP logic technology than for HP logic technology applications. A moderately doped JL MOSFET (1018 cm-3 to 5×1018 cm-3) can further improve LP performance, reduce parameter variability and relax gate workfunction requirement. Dedicated optimizations of underlap regions and sidewall spacers in JL FETs are essential for LP technologies. Recently, JL MOSFET with innovative Shell Doping Profile (SDP) has experimentally demonstrated improved S, higher ION/IOFF ratio, and lower parameter sensitivity than uniformly doped JL transistors, thus indicating favorable prospects for downscaling and LP technology. In conventional JL transistors, due to the identical dopant type (preferably high doping) throughout the semiconductor film, the extension of depletion regions outside the gated portion can take place in the off-state. Consequently, effective channel length (Leff) becomes longer than Lg. An elongated Leff in the subthreshold operating regime can suppress SCEs in these transistors and has the potential for LP technology while enabling downscaling. This unique and inherent property of JL transistors exists in mostly all JL architectures, whether traditional structures [11], modified structures with Gate-Source/Drain (G-S/D) underlap, or novel JL FET with SDP. However, the value of Leff in the subthreshold regime varies in different topologies. The thesis provides comprehensive and dedicated approaches to estimate as well as suppress SCEs in various Double Gate (DG) JL architectures (DG JL with G-S/D underlap and SDP), by adequately capturing Leff in the subthreshold regime. The thesis also identifies critical design parameters that can be optimized for superior short channel performance, thereby providing optimally designed DG JL transistor for LP subthreshold logic applications. A five-region semi-analytical model for subthreshold channel potential is developed to adequately capture Leff for symmetric mode-operated DG JL MOSFET at any gate-underlap length. The five-region model can be adapted into three or four regions depending upon the lateral extent of depletion into the G-S/D underlap. The transfer characteristics obtained from approximate analytical solutions for subthreshold drain current (Ids) are utilized to extract the parameters indicating SCEs (dVth, DIBL and S). The developed model results reasonably agree with simulation data. The thesis presents that channel doping and underlap length are two critical parameters that affect SCEs. An optimally long underlap along with moderate doping (1018 cm-3) can be used as an advantage to improve SCEs at sub-50 nm gate lengths. The thesis develops a semi-analytical model to estimate SCEs for independent gate-operated asymmetric DG structure with G-S/D underlap. The model considers non-identical values for front and back gate workfunctions and oxide thicknesses, and S/D underlap lengths. The modeled Ids, Vth, and S adequately agree with the simulation data. The thesis highlights the role of back gate bias (Vbg), channel doping (Nd) and underlap length (Lun) to improve the device performance through optimization of off-current (IOFF), Vth and S. Results propose an optimum choice of negative Vbg together with moderate Nd and sufficiently long Lun for short channel asymmetric DG JL device. The generalized model formalism in the subthreshold regime can be utilized to optimize the self-aligned DG JL device for LP subthreshold logic applications. The thesis also presents a semi-analytical model for estimating Leff-dependent SCEs in DG JL MOSFET with SDP (referred to as Core-Shell (CS) DG JL MOSFET). The developed model reasonably captures the channel potential and SCEs in CS DG JL MOSFETs for varying Lg, core thickness (Tcore), shell doping (Nd) and biases. The modeled Vth, DIBL and S, derived from the transfer characteristics, are in good agreement with the simulation results. The thesis investigates the impact of Nd and Tcore on the short channel performance of the CS DG JL MOSFET. Results suggest that the moderate Nd – narrow Tcore pair can be preferred over high Nd – wide Tcore for similar SCEs but at reduced Vth sensitivity.