Design and fabrication of MgZnO/CdZnO heterostructures for HFET application

Abstract

This work explores dual ion beam sputtering (DIBS)-grown heterostructure of Magnesium Zinc Oxide and Cadmium Zinc Oxide (MgZnO/CdZnO) for the possibility of achieving high two-dimensional electron gas (2DEG) density (ns) and eventually high values of drain current (Id) in order to develop a low-cost large-area-electronics compatible heterostructure field effect transistor (HFET). The heterostructure MgZnO/CdZnO proposed and exploited in this work is a functional solution to circumvent the limitations presented by the heterostructures of MgZnO/ZnO, Beryllium Zinc Oxide and Zinc Oxide (BeZnO/ZnO), and BeMgZnO/ZnO towards achieving high values of ns. The long-pending challenge with popular MgxZn1-xO/ZnO heterostructure system is the occurrence of phase segregation at high Mg content (x > 0.35) in barrier layer, which limits this heterostructure from achieving high values of ns. To circumvent this limitation, BeyMgxZn1-x-yO as the barrier layer was proposed in the literature that yielded ns comparable to that achieved in the case of Mg0.6Zn0.4O/ZnO heterostructure by utilizing y = 0.2 and x = 0.26. While, BeMgZnO enhances ns in ZnO-based heterostructures for lower Mg content, Be2+ ions leave the substitutional lattice sites when annealed at 400 °C and above. The ohmic contact formation for HFET demands metal contacts at the source and drain regions to be annealed at ≥ 800 °C, which imposes a limitation for utilizing BeMgZnO or BeZnO in the barrier layer. Alloying Cadmium Oxide (CdO) in the buffer ZnO layer reduces the spontaneous polarization of the buffer layer and increase conduction band offset at the barrier-buffer interface. Both these phenomena add up to a possibility of significant enhancement in ns in MgZnO/CdZnO heterostructure over MgZnO/ZnO heterostructure at lower Mg content in the barrier layer. In addition, reports of sputtered ZnO heterostructures yielding 2DEG are available in the literature, while Gallium Nitride (GaN) heterostructures are generally fabricated using costly epitaxial growth mechanisms such as molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD). It can be pointed out that MBE is incompatible with large-area fabrication of electronic devices and systems and MOCVD needs extreme control of multiple growth parameters alongside the precise selection of precursors. Sputtering process, on the other hand, is a user-friendly, cost-effective, and large-area compatible growth technique. Amongst various sputtering techniques, DIBS is notable for producing high-quality thin films with reasonably superior compositional stoichiometry and uniformity as well as better film adhesion over a larger substrate surface area. DIBS-grown MgZnO/ZnO heterostructures have been reported to induce 2DEG with conductance, a product of 2DEG density and carrier mobility, comparable to that in GaN-based heterostructure and higher than that in Gallium Arsenide (GaAs)-based heterostructures. Therefore, this work explores the possibility of achieving high ns and drain current (Id) characteristics for low-cost large-area-electronics compatible DIBS-grown MgZnO/CdZnO heterostructure for HFET application. To achieve this objective, first a physics-based analytical model is developed to estimate the enhancement in ns MgZnO/CdZnO heterostructure can provide over MgZnO/ZnO heterostructure at similar barrier layer thickness and Mg content in barrier layer. Utilizing the developed analytical model, it was demonstrated that up to ~25× higher ns values can be achieved in MgZnO/CdZnO as compared to that in MgZnO/ZnO heterostructure at lower Mg composition of 0.10 in barrier layer for same barrier layer thickness. It was shown that a lower spontaneous polarization in buffer layer due to more electronegative Cd and higher lattice constant of CdZnO which introduces tensile piezoelectric strain in the barrier layer, favorably add up, and increase polarization difference at barrier-buffer interface which eventually enhances ns. This analytical model demonstrated new opportunities to effectively utilize buffer layer properties to significantly improve ns (~4 × 1013 cm-2) in ZnO heterostructures. After analytically establishing possibility of achieving higher ns in MgZnO/CdZnO heterostructure over MgZnO/ZnO heterostructure, the predictions of analytical model were confirmed experimentally by DIBS-grown MgZnO/CdZnO heterostructure. In the experimental report significantly high (~6×) ns in MgZnO/CdZnO heterostructure was achieved as compared to that in MgZnO/ZnO, at lower Mg (≤ 0.15) compositions in barrier MgZnO layer, with both heterostructures grown by dual ion beam sputtering (DIBS) technique. Buffer CdZnO and barrier MgZnO layers were probed separately to investigate carrier density in defect prone sputtered layers prior to development of MgZnO/CdZnO heterostructure. The MgZnO/CdZnO heterostructure was than characterized by capacitance-voltage (C-V) measurement and temperature-dependent Hall measurement to confirm the presence of quantum confined carrier density at barrier-buffer interface. The results from C-V measurement and temperature-dependent Hall measurement suggested that the enhancement in carrier densities in the MgZnO/CdZnO heterostructure over individual MgZnO and CdZnO thin films was probably due to the formation of two-dimensional electron gas (2-DEG). Further after establishing high values of ns in DIBS-grown MgZnO/CdZnO heterostructure, another analytical model was developed to estimate Id characteristics in polycrystalline MgZnO/ZnO and MgZnO/CdZnO-based HFET. The developed model utilized ionized interface states density (Qi) and its interrelationship with the barrier layer thickness (d), Mg content (x), and electron mobility (𝜇) to account for the interface defects and their variations with electrical and physical parameters of polycrystalline heterointerface. The results achieved in this study suggested that the saturation drain current (Idsat) in MgZnO/CdZnO HFET can be comparable to that in MgZnO/ZnO HFET when Qi enhancement is considered along with the reduction in 𝜇. This work extensively explored major relationships of Qi, which governs Id in HFETs, with d and x to convincingly postulate that the experimental Id in polycrystalline MgZnO/ZnO and MgZnO/CdZnO-based HFETs could be a combination of the two extreme cases of Qi dependent and independent on d and x. After the analytical study of polycrystalline MgZnO/CdZnO-based HFET, a DIBS-grown MgZnO/CdZnO-based gateless HFET was fabricated by photolithography. Prior to development of MgZnO/CdZnO-based HFET, the conductance (ns × 𝜇 ) of MgZnO/CdZnO heterostructure was enhanced over MgZnO/ZnO heterostructure by introduction of a 30 nm yttria (Y2O3) spacer layer. Introduction of a crystalline Y2O3 significantly enhanced the crystallinity of the buffer layer CdZnO and reduced the interface roughness at the heterojunction of MgZnO/CdZnO heterostructure. Further, transmission line measurement (TLM) technique was utilized to ascertain metal combination and annealing conditions to attain least specific contact resistivity (𝜌𝑐) for developing source and drain metal contacts. The results suggested that introduction of yttria spacer layer improved the overall conductance of MgZnO/CdZnO up to 3.5 × 1015 V-1s-1 as compared to 9 × 1014 V-1s-1 in non-yttria spacer based MgZnO/CdZnO. After all these optimizations, the drain current-drain voltage (Id-Vd) characteristic of the as as-developed yttria spacer based MgZnO/CdZnO HFET showed high drain current value (~400 mA/mm). The study presented in this work, hence, establishes DIBS-grown MgZnO/CdZnO heterostructure as a viable option for low cost HFETs necessary for fabrication of large scale HFET based power and sensor devices.