MAC interfaces with ethernet PHY

Abstract

With the unexpected rate of growth in technology, demand for a high speed and high performance devices has increased. IP digital Designing is now at a avery challenging state where requirement of complex design is growing exponentially. Designer can now design chips with lakhs of transistors on a single chip. Verilog hardware discription languages provide an ease to develop such complex designs. AMBA bus architecture is one such complex design which can be developed using verilog. The APB which is a part of AMBA bus design is implemented in this project using verilog and verified using testbench. Often, when the chip is manufactured there will be a lot of silicon bugs. These bugs can arise for a number of reasons such as manufacturing defects or improper design etc. These bugs can be anywhere on the chip. To pin point the bugs present in a specific area, additional logic is added to the design. This additional logic will not impact the main functions of the chip. One such logic is the ability for the chip to test itelf. This is called Built in self test (BIST). This comes under “design for Testibility”. A module for this issue is developed in this project. On an Ethernet PHY chip, Data is transferred over data path between the PHY and MAC layers of OSI Model. In the validation stage of the chip these data paths are checked for silicon bugs using BIST engine module discussed in depth. An insight on different media independent interfaces is also given. These interfaces are divided based on the clockspeed, port requirement etc and best features of each interface is highlighted.