Study and analysis of power optimization techniques for high-speed cache memory architecture

Abstract

Power optimization in cache memory is very attractive area of research to achieve data transfer at high speed between the high-speed processor and low speed main memory (DRAM). The processor accesses the main memory through cache memory to enhance system performance. This thesis demonstrates that cache usage is an important measure of performance and power with an emphasis on the order of access to the cache line. In this thesis, we mainly focused on cache memory optimization through L1 data cache memory. For that we did experiment on 32KB size of cache memory architecture with 64B cache size and 4-way set associative cache and divide this 32KB size of cache memory into smaller size of caches using 2KB, 4KB, 8KB and 16KB size of logical banks to organize 32KB memory. After that we compared all 2KB, 4KB, 8KB and 16KB logical banks based on the number of comparators used, number of shared or individual address decoder used, number of multiplexers required in each logical bank. After that we evaluate the miss rate in data transfer, cost in each logical bank organization, bandwidth required in each organization and memory traffic in each organization. Sleep mode finite machine concept is also used as per the Qualcomm memory specs to save the power and in that clock is used only when memory is busy in reading and writing of data, else clock is off as per memory timing specification. With the help of all these observations we decided 4KB and 8KB logical bank organization is better suited for one big 32KB size logical bank organization.