Automation of network on chip design flow and creation of a framework for PPA (power, performance, area) improvement analyses

Abstract

High latency, bandwidth, and throughput requirements have originated the deployment of multi-core processors in SoCs.As the transistor sizes shrink and the IPs(Intellectual Property)used in the chip increases, the quality of service begins to crumble. The conventional cross-bar and bus approach prove to be impotent. Network on the chip is the contemporary communication network technology that facilitated point-to-point communication among the Processing elements providing scalability, high bandwidth and operating frequencies. Design automation has been a vital area of research for at least three decades. Due to the intricacy involved in the system and the increased complexity of the fabrication techniques, chips' design has become a crucial task. Automating the activities involved in the design flow lessens human errors and saves time. For complex architectures like Network-on-chip, the area populated by each sub-element like buffers, interface units, power-related elements, and debug probes is paramount for analysis and planning on design reuse and improvements. A framework is created that visualises the area from the area data files and projects it into different technology nodes for given scaling factors. Debug infrastructure present in the Network-on-chip subsystem captures the time-stamp and hang state data. The debug data dumps are an enormous amount of data to be analysed and identify the cause of hangs; here, a framework is proposed that identifies if the debug register’s data corresponding to the hang state, captures the data lessening the efforts and time invested for debugging. Scaling down the technology node adds complications like more leakage and more static power dissipation, high delays owing to reduced dimensions of wires of interconnect. The shift of focus is now towards integrating electrical interconnect with optical NOC for reducing the issues faced. Owing to the compatibility of Silicon-Photonics with the CMOS technology, ONOC router architecture is proposed, the design flow and its Performance analysis are discussed.