Multi - objective design space exploration in high level synthesis for application specific computing

Abstract

High level synthesis (HLS) has gained rapid dominance in the design flow of application specific computing. In HLS, design space exploration (DSE) is an indispensable part, which plays a vital role during design process. Due to advancement in DSE, the designing of an optimal digital circuit for highly complex applications has become possible. Therefore, this thesis proposed four novel automated DSE methodologies for designing application specific systems (ASP) or hardware accelerators. This thesis solves four different types of problem in DSE: a) Design space exploration problem for data intensive application during power performance trade-off by proposing a novel DSE methodology employing particle swarm optimization (PSO). In addition, a novel model for power metric, a novel fitness function used for design quality assessment, a novel mutation algorithm, a novel end terminal perturbation algorithm to handle boundary outreach problem during exploration have also been proposed through this solution. Moreover, sensitivity analysis of different PSO parameters such as swarm size, inertia weight, acceleration coefficient, and termination condition on multi objective DSE have also been presented in this solution. b) Multi-objective DSE problem for single loop based control and data intensive application by proposing a novel automated methodology for simultaneous exploration of data path and loop unrolling factor (UF) through an integrated multi-dimensional particle encoding process using swarm intelligence. Moreover, to enhance exploration process an estimation model for computation of execution delay of a loop unrolled control and data flow graph (CDFG) (based on a resource configuration visited) without requiring to tediously unroll the entire CDFG for the specified loop value for single loop based application has also been presented. c) DSE problem during area performance trade-off for single loop based CDFG by proposing automated exploration of data path and loop UF together through PSO. d) DSE problem for perfectly nested loop based applications during power performance trade-off by proposing anovel methodology for automated exploration of architecture and UFs for nested loop using particle swarm optimization. Moreover, a model has been derived which directly estimatesthe execution time of nested loop, based on resource constraint and UFs without necessity of tediously unrolling the entire CDFG for the specified UFs values in most cases. The proposed exploration approaches can be applied for designing application specific systems, standalone application specific integrated circuits (ASIC’s), hardware accelerators, or DSP cores. Results of the experiments for proposed approaches on the standard benchmarks indicated improvements in terms of exploration runtime and enhancement of quality of final solution (final cost) when compared to recent approaches.