Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/4633
Title: Reusable intellectual property core protection for both buyer and seller
Authors: Sengupta, Anirban
Roy, Dipanjan
Keywords: Sales;Architectural synthesis;Area overhead;Core design;Design costs;Register allocation;Robust mechanisms;Intellectual property core
Issue Date: 2018
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Sengupta, A., & Roy, D. (2018). Reusable intellectual property core protection for both buyer and seller. Paper presented at the 2018 IEEE International Conference on Consumer Electronics, ICCE 2018, , 2018-January doi:10.1109/ICCE.2018.8326059
Abstract: This paper presents a methodology for IP core protection of CE devices from both buyer's and seller's perspective. In the presented methodology, buyer fingerprint is embedded along seller watermark during architectural synthesis phase of IP core design. The buyer fingerprint is inserted during scheduling phase while seller watermark is implanted during register allocation phase of architectural synthesis process. The presented approach provides a robust mechanisms of IP core protection for both buyer and seller at zero area overhead, 1.1 % latency overhead and 0.95 % design cost overhead compared to a similar approach (that provides only protection to IP seller). © 2018 IEEE.
URI: https://doi.org/10.1109/ICCE.2018.8326059
https://dspace.iiti.ac.in/handle/123456789/4633
ISBN: 9781538630259
Type of Material: Conference Paper
Appears in Collections:Department of Computer Science and Engineering

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