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https://dspace.iiti.ac.in/handle/123456789/4666
Title: | Embedding low cost optimal watermark during high level synthesis for reusable IP core protection |
Authors: | Sengupta, Anirban |
Keywords: | Costs;Integrated circuit design;Reconfigurable hardware;Supply chains;Watermarking;Behavioral level;Future designs;Hardware overheads;Intellectual property cores;IP security;Multi variables;Storage overhead;Time to market;High level synthesis |
Issue Date: | 2016 |
Publisher: | Institute of Electrical and Electronics Engineers Inc. |
Citation: | Sengupta, A., Bhadauria, S., & Mohanty, S. P. (2016). Embedding low cost optimal watermark during high level synthesis for reusable IP core protection. Paper presented at the Proceedings - IEEE International Symposium on Circuits and Systems, , 2016-July 974-977. doi:10.1109/ISCAS.2016.7527405 |
Abstract: | Intellectual property (IP) cores have emerged as a promising solution to the challenges of future design as well as mounting time to market pressure. However, due to increasing globalization of design supply chain, possibility of intervention and typical attacks is on the rise, which therefore mandates protection of IP cores from piracy/counterfeiting even at behavioral level. This paper presents a technique for generating low cost watermarking solution during high level synthesis (HLS) based on multi-variable signature encoding for security of reusable IP cores. The watermark generated by the proposed approach satisfies the following properties: (a) low embedding cost (b) robustness (c) low watermark creation time (d) strong proof of authorship (e) lower hardware overhead. Comparison with similar technique revealed that proposed approach obtains watermarked solution with lower embedding cost with less storage overhead and creation time. © 2016 IEEE. |
URI: | https://doi.org/10.1109/ISCAS.2016.7527405 https://dspace.iiti.ac.in/handle/123456789/4666 |
ISBN: | 9781479953400 |
ISSN: | 0271-4310 |
Type of Material: | Conference Paper |
Appears in Collections: | Department of Computer Science and Engineering |
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