Evaluation of nanoscale MOSFET architectures for low power analog/RF applications

Abstract

Scaling dimensions for new and continuing product cycles has introduced new challenges for transistor design. As the end of the technology roadmap for semiconductors is approaching, new device structures are being investigated as possible replacements for traditional Metal-Oxide- Semiconductor Field Effect Transistors (MOSFETs). This new device technology is expected to be energy efficient, dense, and enable more device function per unit space and time. Analog/RF designers have faced difficulty to scale down the devices as aggressively as logic designers because of the severe degradation in performance which is due to intrinsic and extrinsic parameters. As a result not much attention has been devoted to miniaturization of analog/RF devices as compared to logic applications. This thesis investigates the analog/RF performance of nanoscale architectures like underlap inversion mode MOSFETs, junctionless transistors and tunnel FETs. These devices are aimed to operate at supply voltages of 0.5 V which has enabled by lower subthreshold swing, enhanced gate controllability and reduced parasitic components. Published research work is briefly reviewed to better appreciate the research landscape regarding analog/RF performance of nanoscale MOSFET. Devices fabricated in Silicon-on-Insulator (SOI) technology are investigated as they are the most promising and foundry feasible solution for advancing to the nanoscale MOSFET design and functionality. SOI technology has been widely used for nanoscale regime due to excellent capability to overcome Short-Channel-Effects (SCE). Multi- Gate (MG) SOI MOSFETs exhibit improved short-channel effects immunity. The enhancement of the mobility of carriers in MG MOSFETs is due to volume inversion in which the entire silicon film gets inverted and offers reduced carrier scattering particularly useful for low power applications. MG SOI MOSFETs with enhanced performance still face the issue of low-power operation needed forfuture generation wireless applications and get stuck in design issues related to efficient scaling scenarios where performance should not be compromised. The thesis work starts with a discussion on the gate to source/drain region underlap in classical inversion-mode MOSFET architecture to mitigate issues related to downscaling like parasitic resistances and capacitances. The channel design through source/drain extension region engineering achieves this performance improvement in Double-Gate (DG) SOI technology due to reduction in drain electric field in classical inversion-mode MOSFETs. The design presents a tradeoff between device spacer-width and lateral straggle and thus the performance optimization could be specific to the circuit application. Analog/RF performance of DG MOSFET is investigated through well calibrated device simulations at nanoscale dimensions and. Performance results for analog/RF figure-of-merits (FOM) of the DG structure is presented through optimisation around sweet spot ultra low power regime. In particular the ultra low power (ULP) performance metrics are shown to be improved due to reduction of parasitic components. The work is then extended to evaluate the analog/RF performance metrics in junctionless transistors for low power applications. A junctionless (JL) transistor has the same type of dopants in the source, drain and channel regions. This eliminated the need for costly ultrafast annealing techniques and are easier to fabricate. As a first step, the enhanced performance metrics achieved byjunctionless against classical inversion-mode MOSFETs architecture is attributed to an inherent device underlap, offered by JL devices. This opens up the opportunities available while designing junctionless transistor for optimum analog/RF performance. Design guidelines for junctionless structure is then presented with the help of simulations focusing on spacer width of source/drain extension regions and channel doping to minimize parasitic capacitance and drain electric field. The proposed design is also beneficial for operation around analog sweet spot to achieve higher gain, bandwidth and linearity metrics which overcome the conventional analog design trade-offs. The proposed improved junctionless low power transistor exhibits much lower parameter sensitivity values. Band-to-band tunneling (BTBT) in semiconductors, often viewed as an adverse effect of short channel lengths, had been proposed as a promising current injection mechanism to allow for reduced operating voltages in nanoscale MOSFETs. The conventional lateral tunnel FET in which tunneling occurs from source to channel region due to the gate electric field has shown lower leakage current and enhanced short-channel immunity. These devices show scaling trends indecananometer regime, if optimized with specific band-gap material in source/channel tunneling interface region along with low-κ spacer. Device simulations are used to optimize tunnel FET structures involving vertical tunneling. In a vertical tunnel FET, tunneling is expected to enhance with the alignment of gate electric field and source/channel tunnel junction. Various advantages of a vertical tunnel FET is verified through device simulations over lateral tunnel FET. This includes optimization of gate and drain overlap/underlap region and dielectric-spacer combination in lateral tunnel FET, SixGe1-x channel thickness and Ge mole fraction in hetero-structure vertical tunnel FET. The thesis work offers an assessment of analog/RF performance metrics in emerging MOSFET device architectures for low power applications. The research work has shown that analog trade-off in terms of gain, bandwidth and linearity can be effectively balanced using underlap channel architecture and the same topology can be effectively adapted in junctionless transistors also. Leakage current and parasitic capacitance is found to be still higher in case of both tunnel FETs. Optimised lateral and vertical tunnel FETs showcase high intrinsic gain as compared to both underalap inversion-mode and optimised junctionless MOSFETs. This work provides new perspectives into the operation of emerging MOS devices from an analog/RF domain, and will be useful for benchmarking for analog/RF applications.