Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/4849
Title: Obfuscated Hardware Accelerators for Image Processing Filters - Application Specific and Functionally Reconfigurable Processors
Authors: Sengupta, Anirban
Rathor, Mahendra
Keywords: Acceleration;Computer hardware;Edge detection;Hardware security;Integrated circuit design;Matrix algebra;Reconfigurable hardware;Application specific;Application specific processors;Application-specific processor design;Hardware accelerator architecture;Hardware accelerators;Image processing filters;Reconfigurable processors;Strong securities;Image processing
Issue Date: 2020
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Sengupta, A., & Rathor, M. (2020). Obfuscated hardware accelerators for image processing filters - application specific and functionally reconfigurable processors. IEEE Transactions on Consumer Electronics, 66(4), 386-395. doi:10.1109/TCE.2020.3027760
Abstract: Hardware accelerators are widely used as computationally-intensive cores in consumer electronics (CE) applications. However security and speed of such hardware accelerators, that are responsible for computing data-intensive tasks, play an important role in improving consumer experience in terms of safety and performance. This article presents novel low power multi-modal hardware accelerator architectures viz. application specific processor and functionally reconfigurable processor for image processing filter of $3\times 3$ kernel matrix size. In the proposed functionally reconfigurable processor of $3\times 3$ filter, the same design can be used for five different image processing filters - blurring, sharpening, vertical embossment, horizontal embossment and Laplace edge detection, by varying control input. Further, application specific processor designs of these five types of $3\times 3$ filters are also presented in this article. Additionally, application specific processor architecture of $5\times 5$ filter kernel matrix size is also reported in this article. The results confirm that the proposed hardware accelerators achieve strong security and low design cost. © 1975-2011 IEEE.
URI: https://doi.org/10.1109/TCE.2020.3027760
https://dspace.iiti.ac.in/handle/123456789/4849
ISSN: 0098-3063
Type of Material: Journal Article
Appears in Collections:Department of Computer Science and Engineering

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