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https://dspace.iiti.ac.in/handle/123456789/5167
| Title: | Architecture evaluation for standalone and embedded 1t-dram |
| Authors: | Navlakha, Nupur Kranti, Abhinav |
| Keywords: | High temperature applications;VLSI circuits;Accumulation modes;Architecture evaluation;High temperature;Inversion modes;Performance metrics;Retention time;Standalone applications;Transistor architecture;Dynamic random access storage |
| Issue Date: | 2019 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Raza Ansari, M. H., Navlakha, N., Lin, J. -., & Kranti, A. (2019). Architecture evaluation for standalone and embedded 1t-dram. Paper presented at the 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019, doi:10.1109/VLSI-TSA.2019.8804667 |
| Abstract: | This paper analyzes different transistor architectures (inversion mode (IM), accumulation mode (AM) and junctionless (JL)) for standalone as well as embedded DRAM. The performance metrics (retention time (RT), sense margin (SM), current ratio (CR) and write time (WT)) of JL based 1T-DRAM can be improved through stacked JL (SJL) and core-shell (CS) topologies, which separate conduction and storage regions. Results including gate length scalability (25 nm) and high temperature (125 °C) operation indicate the preference for SJL for standalone applications while CS architecture for embedded DRAM. © 2019 IEEE. |
| URI: | https://doi.org/10.1109/VLSI-TSA.2019.8804667 https://dspace.iiti.ac.in/handle/123456789/5167 |
| ISBN: | 9781728109428 |
| Type of Material: | Conference Paper |
| Appears in Collections: | Department of Electrical Engineering |
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