Please use this identifier to cite or link to this item:
https://dspace.iiti.ac.in/handle/123456789/5174
| Title: | Performance assessment of TFET architectures as 1T-DRAM |
| Authors: | Navlakha, Nupur Kranti, Abhinav |
| Keywords: | Commerce;Economic and social effects;Memory architecture;Microelectronics;Tunnel field effect transistors;1t drams;Current ratios;Device performance;Impact of temperatures;Optimal architecture;Performance assessment;Retention time;TFET;Dynamic random access storage |
| Issue Date: | 2019 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Navlakha, N., Ansari, M. H. R., Lin, J. -., & Kranti, A. (2019). Performance assessment of TFET architectures as 1T-DRAM. Paper presented at the 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, doi:10.1109/S3S.2018.8640200 |
| Abstract: | An assessment of Tunnel FET (TFET) architectures for capacitorless dynamic memory applications is presented through composite metrics to balance various trade-offs while regulating hole distribution to determine sense margin, retention time and current ratio. The impact of temperature, bias and scalability on device performance is also investigated. Results highlight the potential of TFET to overcome various trade-offs through optimal architecture, and achieve enhanced composite metrics at sub-100 nm gate lengths. (0) © 2018 IEEE. |
| URI: | https://doi.org/10.1109/S3S.2018.8640200 https://dspace.iiti.ac.in/handle/123456789/5174 |
| ISBN: | 9781538676264 |
| Type of Material: | Conference Paper |
| Appears in Collections: | Department of Electrical Engineering |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
Altmetric Badge: