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https://dspace.iiti.ac.in/handle/123456789/5269
| Title: | Design optimization of tunnel FET for dynamic memory applications |
| Authors: | Navlakha, Nupur Kranti, Abhinav |
| Keywords: | Dynamic random access storage;Electron devices;Electron tunneling;MOS devices;Scalability;Solid state devices;Tunnel field effect transistors;Band to band tunneling;Design optimization;Double gate;Dynamic memory;Innovative design;Retention characteristics;Retention time;Tunnel field-effect transistors (TFET);Field effect transistors |
| Issue Date: | 2017 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Navlakha, N., Lin, J. -., & Kranti, A. (2017). Design optimization of tunnel FET for dynamic memory applications. Paper presented at the EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits, , 2017-January 1-2. doi:10.1109/EDSSC.2017.8126454 |
| Abstract: | The work reports on an innovative design to improve the scalability of misaligned Double Gate (DG) Tunnel Field Effect Transistor (TFET) for operation as dynamic memory. The design optimization is achieved through use of lateral gap on both edges of back gate (G2) that reduces Band-To-Band Tunneling (BTBT) and enhances Retention Time (RT) by a factor of -3. The front gate responsible for read mechanism can be scaled down to 75 nm while G2 can be scaled until 40 nm. The investigation highlights better scalability and improved retention characteristics. © 2017 IEEE. |
| URI: | https://doi.org/10.1109/EDSSC.2017.8126454 https://dspace.iiti.ac.in/handle/123456789/5269 |
| ISBN: | 9781538629079 |
| Type of Material: | Conference Paper |
| Appears in Collections: | Department of Electrical Engineering |
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