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| Title: | Vertical Channel Capacitor-less One-Transistor DRAMs with a pass-way Trench for improving Retention Time |
| Authors: | Kranti, Abhinav |
| Keywords: | Integrated circuits;Capacitor-less;Conventional structures;Device fabrications;Gate-all-around;Memory operations;One-transistor DRAM;Programming window;Vertical channels;Dynamic random access storage |
| Issue Date: | 2017 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Hsu, T. -., Lin, J. -., Huang, C. -., Lin, C. -., Kranti, A., Yu, C. -., . . . Lin, P. -. (2017). Vertical channel capacitor-less one-transistor DRAMs with a pass-way trench for improving retention time. Paper presented at the 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings, 869-871. doi:10.1109/ICSICT.2016.7999065 |
| Abstract: | In this paper, we propose a capacitor-less 1T-DRAM structure with the pass-way trench for improving the Retention Time (RT). We have improved the device fabrication process to form the pass-way trench of the structure which combines the Vertical Channel and the Gate-All-Around structure (PTVCT). The memory operation and its attractive performance in terms of programming window, retention time, and writing time are investigated. The pass-way trench improves programming window and retention time of the structure in comparison to conventional structure. © 2016 IEEE. |
| URI: | https://doi.org/10.1109/ICSICT.2016.7999065 https://dspace.iiti.ac.in/handle/123456789/5294 |
| ISBN: | 9781467397179 |
| Type of Material: | Conference Paper |
| Appears in Collections: | Department of Electrical Engineering |
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