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https://dspace.iiti.ac.in/handle/123456789/5840
| Title: | Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design |
| Authors: | Singh, Pooran Sharma, Vishal Vishvakarma, Santosh Kumar |
| Keywords: | Cells;Cytology;Electric power factor correction;Field programmable gate arrays (FPGA);Integrated circuit design;Static random access storage;Table lookup;Cell stability;Leakage power;Look up table;Macro block;SRAM Cell;Static noise margin;Ultra low power;Feedback |
| Issue Date: | 2018 |
| Publisher: | Elsevier B.V. |
| Citation: | Singh, P., Reniwal, B. S., Vijayvargiya, V., Sharma, V., & Vishvakarma, S. K. (2018). Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design. Integration, 62, 1-13. doi:10.1016/j.vlsi.2018.03.006 |
| Abstract: | To improve leakage power along with better cell stability, a 10 T SRAM cell is presented in this paper. Further, the proposed cell is used to implement a 6-input look up table (LUT) of FPGA and a 2 kb SRAM macroblock. The proposed cell achieves better results in terms of write static noise margin by 1.66 ×, 1.8 ×; read static noise margin by 3.8 ×, 1.37 ×; write trip point by 2 ×, 2 × as compared to conventional (C) 6 T, read decoupled (RD) 8 T SRAM, respectively. The leakage power is also reduced to 0.07 ×, and 0.43 × as compared C6T and RD8T SRAM, respectively at 0.3 V VDD. © 2018 |
| URI: | https://doi.org/10.1016/j.vlsi.2018.03.006 https://dspace.iiti.ac.in/handle/123456789/5840 |
| ISSN: | 0167-9260 |
| Type of Material: | Journal Article |
| Appears in Collections: | Department of Electrical Engineering |
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