Doping Dependent Assessment of Accumulation Mode and Junctionless FET for 1T DRAM

Abstract

This paper demonstrates the use of double-gate accumulation mode (AM) and junctionless (JL) transistors for dynamic memory applications at 85 °C. The doping dependent assessments of AM and JL devices include an analysis of storage volume, carrier lifetime, and depth of potential well to determine characteristics of Dynamic Random Access Memory (DRAM). This paper shows significant impact of carrier lifetime for channel doping (Nd) ≤ 1018 cm-3 on Retention Time (RT), while the depth of potential well is more critical at higher doping (>1018 cm-3). RT of 2.5 s at 85 °C and 4.5 s at 27 °C is achieved for gate length (Lg) of 400 nm with Nd = 1017 cm-3 which reduces to 90 ms at 85 °C for Lg = 25 nm. This paper discusses the storage volume (Lg × fil thickness for a fixed volume with width of 1 μm) optimization to attain maximum retention. Insights and guidelines, as a function of doping and device dimensions, are outlined for dynamic memory applications. © 1963-2012 IEEE.