Retention and Scalability Perspective of Sub-100-nm Double Gate Tunnel FET DRAM

Abstract

This paper reports on the design optimization of double gate (DG) tunnel FET (TFET) for dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral spacing (Lgap) between the gates, and an underlap region (Lun) between drain and back gate reduces state '0' degradation, which along with optimal biases, results in an improved Retention Time (RT) at 85 °C. The systematic design optimization increases RT from 80 to 300 ms with the use of Lgap at 85 °C, which can be further improved to 600 ms with the introduction of Lun. The careful investigation shows the back gate scaled down to 25 nm with a front gate region of 100 nm, and operation even at elevated temperatures (125 °C). The insights into DG TFET DRAM operation in terms of individual as well as total lengths highlights the RT enhancement by a factor of 3 with constant total length (200 nm) and an improved scalability with total length scaled down to 160 nm. This paper provides new opportunities to realize TFET-based DRAM with improved RT, scalability, and high temperature operation. © 2017 IEEE.