Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5999
Title: Improvement of short channel performance of junction-free charge trapping 3D NAND flash memory
Authors: Vishvakarma, Santosh Kumar
Keywords: Memory architecture;MOS devices;NAND circuits;Threshold voltage;3-d nand flash memory;Channel engineering;Doping concentration;Drain-induced barrier lowering;Short-channel effect;Short-channel performance;Subthreshold swing;Threshold voltage roll-off;Flash memory;Article;depletion;diffusion;doping;electric potential;memory;memory cell;physical model;retention time;scale up;simulation
Issue Date: 2017
Publisher: Institution of Engineering and Technology
Citation: Gupta, D., & Vishvakarma, S. K. (2017). Improvement of short channel performance of junction-free charge trapping 3D NAND flash memory. Micro and Nano Letters, 12(1), 64-68. doi:10.1049/mnl.2016.0641
Abstract: This work investigates the effect of channel engineering on the short channel performance of considered sub-20-nm 3D NAND flash memory. Here, the threshold voltage roll-off (ΔVth), subthreshold swing and drain induced barrier lowering metrics is studied to evaluate the short channel effects (SCEs) for the examined device. The effect of variation in doping density on SCEs of proposed channel engineered NAND flash memory is also studied. Based on the observation, a thin layer of high doping concentration in the centre of the channel, covering 25% of channel area, has been found to improve the SCE of NAND flash memory compared with the device with uniform channel doping while maintaining sufficient drive current. © The Institution of Engineering and Technology 2016.
URI: https://doi.org/10.1049/mnl.2016.0641
https://dspace.iiti.ac.in/handle/123456789/5999
ISSN: 1750-0443
Type of Material: Journal Article
Appears in Collections:Department of Electrical Engineering

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