Browsing by Author Kachave, Deepak

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Showing results 1 to 15 of 15
Issue DateTitleAuthor(s)
2019Digital Processing Core Performance Degradation Due to Hardware Stress AttacksKachave, Deepak; Sengupta, Anirban
2018Effect of NBTI stress on DSP cores used in CE devices: Threat model and performance estimationKachave, Deepak; Sengupta, Anirban; Neema, Shubha; Harsha, Panugothu Sri
2019Fault-Tolerant DSP Core Datapath Against Omnidirectional Spatial Impact of SETKachave, Deepak; Sengupta, Anirban
2018Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesisSengupta, Anirban; Kachave, Deepak
2016Generating multi-cycle and multiple transient fault resilient design during physically aware high level synthesisSengupta, Anirban; Kachave, Deepak
2018Integrating compiler driven transformation and simulated annealing based floorplan for optimized transient fault tolerant DSP coresSengupta, Anirban; Kachave, Deepak
2016Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processorsKachave, Deepak; Sengupta, Anirban
2017Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesisSengupta, Anirban; Kachave, Deepak
2019Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust LockingSengupta, Anirban; Kachave, Deepak; Roy, Dipanjan
2017Protecting ownership of reusable IP core generated during high level synthesisKachave, Deepak; Sengupta, Anirban
2018Reliability and threat analysis of NBTI stress on DSP coresSengupta, Anirban; Kachave, Deepak; Neema, Shubha; Panugothu, Sri Harsha
2018Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters]Kachave, Deepak; Sengupta, Anirban
2018Spatial and Temporal Redundancy for Transient Fault-Tolerant DatapathSengupta, Anirban; Kachave, Deepak
2019-04-16Transient fault reliability and security of IP coresSengupta, Anirban; Kachave, Deepak
2019Transient fault secured/tolerant architecture for DSP coreKachave, Deepak; Sengupta, Anirban