Low power CMOS integrated circuits for phase-locked loop frequency synthesizers

Abstract

Modern Systems-on-Chip (SoCs) integrate various subsystems on a single chip operating at different clock speeds. Clocking support to these subsystems is provided by numerous Phase Locked Loops which take off-chip crystal output as a reference and generate high-speed on-chip clock signal providing multiple clocks to SoC. Figure 1.1 shows an example of such SoC which boasts ⇠20 PLLs for clock generation and accounts for 7% of total SoC power [1]. The SoC is made up of elements such as the CPU, GPU, DDR, PCIe, and others that operate at frequencies between a few MHz and GHz. One of SoC’s serial link communication systems, PCIe operates at a very high speed and has stringent noise performance specifications for its input and output clock signals.