Feasibility assessment of steep switching in silicon and germanium junctionless transistors

Abstract

Moore’s law in conjunction with Dennard’s scaling theory has enabled the semiconductor industry to significantly improve the performance of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) by enhancing the functionality per unit area [1]. In general, the logic operation of a transistor is characterized by switching from off-to-on state, with the transition from one logic state to another is characterized by a parameter known as Subthrehold swing (S-swing), which describes the rate of change of drain current with respect to gate bias and is equal to the thermal limit ~(kT/q)ln(10), where k is the Boltzmann constant, T is the temperature, and q is the electronic charge [2]. The conventional minimum value of S-swing is limited to 60 mV/decade at room temperature, thereby implying a minimum of 60 mV should be applied at the gate to increase the drain current by a decade. Since downscaling of transistor is aimed to densely arrange more number of devices per unit area, the consequential increase in the static power dissipation due to non-scalability of the supply voltage and S-swing below 60 mV/decade [2] limits the performance of MOSFETs. Hence, transistors which exhibit S-swing lower than 60 mV/decade are highly desirable.