Browsing by Author Nirala, Rohit Kumar
Showing results 1 to 7 of 7
| Issue Date | Title | Author(s) |
| 2023 | Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications | Nirala, Rohit Kumar; Roy, Arghya Singha; Semwal, Sandeep; Rai, Nivedita; Kranti, Abhinav |
| 2023 | Architecture Dependent Constraint-Aware RFET Based 1T-DRAM | Semwal, Sandeep; Nirala, Rohit Kumar; Rai, Nivedita; Kranti, Abhinav |
| 2024 | Energy and Disturbance Analysis of 1T-DRAM With Nanowire Gate-All-Around RFET | Nirala, Rohit Kumar; Semwal, Sandeep; Kranti, Abhinav |
| 2024 | Extremely High Noise Margin and Low Leakage in ULP Circuits with NCFETs | Semwal, Sandeep; Nirala, Rohit Kumar; Kranti, Abhinav |
| 2023 | Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor | Rai, Nivedita; Semwal, Sandeep; Nirala, Rohit Kumar; Kranti, Abhinav |
| 2024 | Quantum Confinement Imposed Constraints in ULP Circuits with Junctionless FET | Semwal, Sandeep; Rai, Nivedita; Nirala, Rohit Kumar; Kranti, Abhinav |
| 2022 | Sensitivity implications for programmable transistor based 1T-DRAM | Nirala, Rohit Kumar; Semwal, Sandeep; Bhuvaneshwari, Y. V.; Rai, Nivedita; Kranti, Abhinav |
