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IDR@IIT Indore
Browsing by Author Vishvakarma, Santosh Kumar
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Showing results 1 to 20 of 192
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Issue Date
Title
Author(s)
2020
A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture
Raut, Gopal
;
Shah, Ambika Prasad
;
Sharma, Vishal
;
Rajput, Gunjan
;
Vishvakarma, Santosh Kumar
2016
A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations
Kushwaha, C. B.
;
Vishvakarma, Santosh Kumar
2018
A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for Internet of Things (IoT) applications
Sharma, Vishal
;
Gopal, Maisagalla
;
Singh, Pooran
;
Vishvakarma, Santosh Kumar
2021
An accurate and noninvasive skin cancer screening based on imaging technique
Rajput, Gunjan
;
Agrawal, Shashank
;
Raut, Gopal
;
Vishvakarma, Santosh Kumar
2018
Analog/RF characteristics of a 3D-Cyl underlap GAA-TFET based on a Ge source using fringing-field engineering for low-power applications
Shah, Ambika Prasad
;
Vishvakarma, Santosh Kumar
2016
Analogue/RF performance attributes of underlap tunnel field effect transistor for low power applications
Singh, Pooran
;
Vishvakarma, Santosh Kumar
2015
Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET
Vishvakarma, Santosh Kumar
2017-10-09
Analysis of charge trap nand flash memory for improved reliability
Vishvakarma, Santosh Kumar
;
Gupta, Deepika
2013
Analysis of crossover point and threshold voltage for triple gate MOSFET
Vishvakarma, Santosh Kumar
2017
Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device Geometry
Vishvakarma, Santosh Kumar
;
Trivedi, Priyal
2017
Analysis of single-trap-induced random telegraph noise on asymmetric high-k spacer FinFET
Vishvakarma, Santosh Kumar
2014
Analysis of stability issues and power efficiency of symmetric and asymmetric low power nanoscaled SRAM cells
Gupta, Anupreet
;
Anwer, Hajra
;
Reniwal, Bhupendra Singh
;
Vishvakarma, Santosh Kumar
2017
Analysis of trap-assisted tunnelling in asymmetrical underlap 3D-cylindrical GAA-TFET based on hetero-spacer engineering for improved device reliability
Vishvakarma, Santosh Kumar
2012
Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions
Vishvakarma, Santosh Kumar
2018
Analytical modeling of split-gate junction-less transistor for a biosensor application
Vishvakarma, Santosh Kumar
2022
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array
Vishvakarma, Santosh Kumar
2019-06-27
Architecture and CAD for emerging technologies
Vishvakarma, Santosh Kumar
;
Kumar, Akash
;
Pallab, Nath
2025
Area-Optimized 2D Interleaved Adder Tree Design for Sparse DCIM Edge Processing
Sankhe, Akash
;
Lokhande, Mukul
;
Sharma, Radheshyam
;
Vishvakarma, Santosh Kumar
2019
ASIC Implementation of Biologically Inspired Spiking Neural Network
Rajput, Gunjan
;
Raut, Gopal
;
Khan, Sajid
;
Gupta, Neha
;
Behor, Ankur
;
Vishvakarma, Santosh Kumar
2019
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM
Singh, Pooran
;
Vishvakarma, Santosh Kumar