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Browsing by Author Semwal, Sandeep

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Showing results 1 to 20 of 20
Issue DateTitleAuthor(s)
2023-12-01Analysis of ferroelectric gate stack induced steep switching and negative differential resistance in MOSFET for ultra low power applicationsKranti, Abhinav; Semwal, Sandeep
2023Analytical modeling of architecture dependent atypical scaling trends in metal-Hf0.5Zr0.5O2-metal-SiO2-Si negative capacitance transistorsSemwal, Sandeep; Kranti, Abhinav
2023Analytical modeling of negative capacitance transistor based ultra low power Schmitt triggerKeerthi, Guntupalli; Semwal, Sandeep; Kranti, Abhinav
2023Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applicationsNirala, Rohit Kumar; Roy, Arghya Singha; Semwal, Sandeep; Rai, Nivedita; Kranti, Abhinav
2023Architecture Dependent Constraint-Aware RFET Based 1T-DRAMSemwal, Sandeep; Nirala, Rohit Kumar; Rai, Nivedita; Kranti, Abhinav
2024Energy and Disturbance Analysis of 1T-DRAM With Nanowire Gate-All-Around RFETNirala, Rohit Kumar; Semwal, Sandeep; Kranti, Abhinav
2024Extremely High Noise Margin and Low Leakage in ULP Circuits with NCFETsSemwal, Sandeep; Nirala, Rohit Kumar; Kranti, Abhinav
2021Ferroelectric Thickness Dependent Characteristics of Negative Capacitance TransistorsSemwal, Sandeep; Kranti, Abhinav
2021Improved Mobility Extraction Methodology for Reconfigurable Transistors Considering Resistive Components and Effective Drain BiasMane, Somesh; Semwal, Sandeep; Kranti, Abhinav
2022Incorporating Quantum Effects in Ultralow Power (ULP) Subthreshold Logic Design With Junctionless Nanowire TransistorRai, Nivedita; Ahuja, Khushboo; Semwal, Sandeep; Kranti, Abhinav
2022An Insightful Assessment of 1T-DRAM with Misaligned Polarity Gate in RFETRoy, Arghya Singha; Semwal, Sandeep; Kranti, Abhinav
2023Insights Into Parasitic Capacitance and Reconfigurable FET Architecture for Enhancing Analog/RF MetricsDeshpande, Aakash Ashutosh; Semwal, Sandeep; Kranti, Abhinav
2021Insights into unconventional behaviour of negative capacitance transistor through a physics-based analytical modelSemwal, Sandeep; Kranti, Abhinav
2020Limits on Hysteresis-Free Sub-60 mV/Decade Operation of MFIS Nanowire TransistorSemwal, Sandeep; Reddy, Veldanda Pranay; Jaiswal, Nivedita; Kranti, Abhinav
2021A metal–ferroelectric–insulator–semiconductor transistor perspective: Nanowire or planar architecture?Semwal, Sandeep; Kranti, Abhinav
2023Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire TransistorRai, Nivedita; Semwal, Sandeep; Nirala, Rohit Kumar; Kranti, Abhinav
2024Quantum Confinement Imposed Constraints in ULP Circuits with Junctionless FETSemwal, Sandeep; Rai, Nivedita; Nirala, Rohit Kumar; Kranti, Abhinav
2022Sensitivity implications for programmable transistor based 1T-DRAMNirala, Rohit Kumar; Semwal, Sandeep; Bhuvaneshwari, Y. V.; Rai, Nivedita; Kranti, Abhinav
2021Ultra-low-power subthreshold logic with germanium junctionless transistorsShrivas, Pradeep; Jaiswal, Nivedita; Semwal, Sandeep; Kranti, Abhinav
2022Unconventional VTC of subthreshold inverter with MFMIS negative capacitance transistor: An analytical modelling framework with implications for ultralow power logic designSemwal, Sandeep; Kranti, Abhinav
Showing results 1 to 20 of 20