IDR@IIT Indore: Browsing DSpace

Browsing by Author Navlakha, Nupur

Jump to: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
or enter first few letters:

Showing results 1 to 20 of 22 next >

Issue Date	Title	Author(s)
2019	1T DRAM with vertically stacked n-oxide-p architecture	Navlakha, Nupur; Kranti, Abhinav
2019	1T-DRAM with Shell-Doped Architecture	Navlakha, Nupur; Kranti, Abhinav
2019	Architecture evaluation for standalone and embedded 1t-dram	Navlakha, Nupur; Kranti, Abhinav
2017	Design optimization of tunnel FET for dynamic memory applications	Navlakha, Nupur; Kranti, Abhinav
2018	Doping Dependent Assessment of Accumulation Mode and Junctionless FET for 1T DRAM	Navlakha, Nupur; Kranti, Abhinav
2020	Double-Gate Junctionless 1T DRAM with Physical Barriers for Retention Improvement	Navlakha, Nupur
2018	Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory	Navlakha, Nupur; Kranti, Abhinav
2018	High Retention with n-Oxide-p Junctionless Architecture for 1T DRAM	Navlakha, Nupur; Kranti, Abhinav
2016	Improved Retention Time in Twin Gate 1T DRAM with Tunneling Based Read Mechanism	Navlakha, Nupur; Kranti, Abhinav
2019	Improving charge retention in capacitorless DRAM through material and device innovation	Navlakha, Nupur; Kranti, Abhinav
2016	Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering	Navlakha, Nupur; Kranti, Abhinav
2017	Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application	Navlakha, Nupur; Kranti, Abhinav
2019	Investigation of junctionless transistor based dram	Navlakha, Nupur; Kranti, Abhinav
2017	Optimization of back gate workfunction, alignment and bias for charge retention in TFET based DRAM	Navlakha, Nupur; Kranti, Abhinav
2017	Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability	Navlakha, Nupur; Kranti, Abhinav
2019	Performance assessment of TFET architectures as 1T-DRAM	Navlakha, Nupur; Kranti, Abhinav
2018-07-24	Performance assessment of tunneling based transisstors for capacitorless dynamic memory applications	Kranti, Abhinav; Navlakha, Nupur
2018	Physical Insights on Junction Controllability for Improved Performance of Planar Trigate Tunnel FET as Capacitorless Dynamic Memory	Navlakha, Nupur; Kranti, Abhinav
2019	Raised Body Doping-Less 1T-DRAM with Source/Drain Schottky Contact	Navlakha, Nupur; Kranti, Abhinav
2017	Retention and Scalability Perspective of Sub-100-nm Double Gate Tunnel FET DRAM	Navlakha, Nupur; Kranti, Abhinav

Showing results 1 to 20 of 22 next >